The present invention relates generally to digital and mixed-signal circuit devices and, more particularly, to a master bias current generating circuit with decreased sensitivity to silicon process variation.
In typical CMOS analog and mixed-signal analog-digital chips, such as imaging products, power management products, and biomedical products, there is a need for a circuit to generate a master bias current. This master bias current generator produces a reference current used in feeding the currents to all or most of the analog blocks, such as operational amplifiers, digital-to-analog converters, and analog-to-digital converters, oscillators, buffers, etc.
As a stand-alone block, the master bias current generator plays an important role in any mixed-signal chip. The functionality, speed, and accuracy of all other analog blocks, such as operational amplifiers, depend on the current produced by the master bias current generator. Before any block is turned on for processing signals, the master bias current generator must be available to produce the current needed. Over the operating temperature variation range of the device (e.g., commercial: −30° C. to 70° C., industrial: −40° C. to 85° C., or military: −55° C. to 125° C.), the master bias current generator must produce a current which is proportional to temperature. The produced master bias current should preferably have a substantially small variation due to variation in the power supply, commonly referred to as power supply rejection ratio. Also, it is desirable to have a master bias current generator that produces a current that is substantially insensitive to silicon process variation.
FIG. 1 illustrates a prior art master bias current generator circuit 100. As seen in FIG. 1, the master bias current generator circuit 100 includes a current generating portion 105 that generates the master bias current, and a current replicating portion 110 that replicates and scales the master bias current so that it may be provided to an analog block of the associated device. Although only one replicating portion 110 is show, a typical device will include many replicating portions to distribute the master bias current to its consumers. The generating portion 105 includes a PMOS current source 115 including transistor 120 and diode-connected transistor 125 and an NMOS current source 130 including a diode-connected transistor 135 and a transistor 140. The complementary PMOS and NMOS current sources 115, 130 cause an equal current to flow into two diode-connected substrate PNP transistors 145, 150.
Typically, the PNP transistors 145, 150 have areas that are multiples of one another. For example, the transistor 150 is commonly eight times larger than the transistor 145. A resistor 155 having a resistance of R is provided between the transistor 140 and the PNP transistor 150. The resistor 155 is realized on chip using a polysilicon layer or an N-well resistor. Variations of prior art master bias circuits include cascoded PMOS and/or NMOS current sources, wide swing biased current sources, or an operational amplifier in place of the NMOS current source 130.
In all these prior art circuits, the generating portion 105 of the master bias current generator circuit 100 provides a reference current, IREF, that flows into the diode-connected PNP transistors 145, 150. Often, the master bias current generator circuit 100 is designed to have the same reference current flowing into both diode-connected PNP transistors 145, 150. However, in some cases, the master bias current generator circuit 100 may configured such that the current passing through one transistor 145 is a multiple of the current passing through the other 150. This scaling may be accomplished by varying the aspect ratios of the PMOS transistors 120, 125 in the PMOS current source 115, as is known to those of ordinary skill in the art.
The replicating portion 110 produces a current which is directly proportional to IREF. The replicating portion 110 includes PMOS transistors 155, 160 having their gate terminals coupled to the gate terminals of the corresponding PMOS transistors 120, 125 in the current generating portion 105 and diode connected NMOS transistors 170, 175. Typically, the output current generated by the replicating portion 110 is an integer scaling of IREF. Generally, the scaling is proportional to the ratio of the aspect ratio (W/L) of the transistors 160, 165 to that of the transistors 120, 125 in the generating portion 105.
In the basic architecture in FIG. 1, assuming that the IREF currents in both sides of the current source are identical, and the emitter area of the PNP transistor 150 is M times the emitter area, A, of the PNP transistor 145, then IREF current can be written as:
                              I          REF                =                                                            V                T                            R                        ⁢                          Ln              ⁡                              (                                                      M                    ×                    A                                    A                                )                                              =                                                    V                T                            R                        ⁢                          Ln              ⁡                              (                M                )                                                                        (        1        )            where VT represents the characteristic thermal voltage (e.g., approximately 26 mV at room temperature).
In typical semiconductor processes, the performance of parameter in a circuit that is ratio of two elements such as ratio of capacitor values, ratio of resistor values, or ratio of areas, etc. is relatively insensitive to process variation. Hence, the variation of IREF due to variations in the emitter areas of the PNP transistors 145, 150 (i.e., A and M×A) is insignificant. It is for just this reason that, the emitter area of the transistor 150 is an integer multiple of the emitter area of the transistor 145.
However, one significant limitation of the prior art master bias current generator 100 arises from the fact that the reference current is a direct function of the absolute resistance, R, of the on-chip resistor 155. As this resistor 155 is realized using a polysilicon layer, source-drain diffusion layer, or N-well resistor, any variation in the absolute resistance is directly inversely related to the reference current produced. In a typical CMOS process, variation in the absolute value of a resistor made of polysilicon can be approximately ±15-20%. In some semiconductor processes, this variation may even be as much as ±30-35%, depending upon the layer used to realize the resistor. This relatively large level of variation may be unacceptable for a particular implementation.
Various techniques for reducing the variation arising from the resistor. In one technique, an external resistor may be used. However, such an external resistor is costly due to the need for an external component and two additional external pads on the device. Another technique is to use a trimming method that allows circuits to be altered to affect the overall resistance. The resistance may be adjusted using a fuse or laser trimming to reduce variation of the current. However, the trimming technique is also costly due to the increased circuit complexity and labor associated with the trimming process.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.